Optimal design of junctionless double gate vertical MOSFET using hybrid  Taguchi-GRA with ANN prediction

K. E. Kaharudin; F. Salehuddin; A. S. M. Zain; Ameer F. Roslan

doi:10.15282/jmes.13.3.2019.16.0442

Authors

K. E. Kaharudin MiNE, CeTRI, Faculty of Electronics and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia, Phone: +6062702361; Fax: +6062701045
F. Salehuddin MiNE, CeTRI, Faculty of Electronics and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia, Phone: +6062702361; Fax: +6062701045
A. S. M. Zain MiNE, CeTRI, Faculty of Electronics and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia, Phone: +6062702361; Fax: +6062701045
Ameer F. Roslan MiNE, CeTRI, Faculty of Electronics and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia, Phone: +6062702361; Fax: +6062701045

DOI:

https://doi.org/10.15282/jmes.13.3.2019.16.0442

Keywords:

Channel doping, channel length, pillar thickness, source/drain doping

Abstract

Random parameter variations have been an influential factor that deciding the performance of a metal-oxide-semiconductor field effect transistor (MOSFET), especially in nano-scale regime. Thus, controlling the variation of those parameters becomes extremely crucial in order to attain an acceptable performance of an ultra-small MOSFET. This paper proposes an approach to optimally design a n-type junctionless double-gate vertical MOSFET (n-JLDGVM) via hybrid Taguchi-grey relational analysis (GRA) with artificial neural networks (ANN) prediction. The device is designed using a combination of 2-D simulation tools (Silvaco) and hybrid Taguchi-GRA with a well-trained ANN prediction. The investigated device parameters consist of channel length (L_ch), pillar thickness (T_p), channel doping (N_ch) and source/drain doping (N_sd). The optimized design parameters of the device demonstrate a tolerable magnitude of on-state current (I_ON), off-state current (I_OFF), on-off ratio, transconductance (g_m), cut-off frequency (f_T) and maximum oscillation frequency (f_max), measured at 2344.9 µA/µm, 2.53 pA/µm, 927 x 10⁶, 4.78 mS/µm, 121.5 GHz and 2469 GHz respectively.

References

Ramakrishnan H. Variability: Analysis and Impact on Circuit Response. 2009.

ITRS. International Technology Roadmap Semiconductor. 2013.

Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, and Wong HP. Device Scaling Limits of Si MOSFETs and Their Application Dependencies. Proceeding of IEEE. 2001;89(3):259–288.

Bedell SW, Majumdar A. Ott JA, Arnold J, Fogel K, Koester SJ and Sadana DK. Mobility scaling in short-channel length strained Ge-on-insulator P-MOSFETs. IEEE Electron Device Letter. 2008;29(7):811–813.

Pradhan KP, Mohapatra SK, and Sahu PK. Impact of Channel and Metal GateWork Function on GS-DG MOSFET: A Linearity Analysis. ECS Journal of Solid State Science and Technology. 2015;4(9):1–5.

Zain ASM. Scaling and Variability in Ultra Thin Body Silicon on Insulator (UTB SOI) MOSFETs. University of Glasgow. 2013.

Rezali FA, Mazhar M, Aida N, Othman F, and Muhamad SW. Performance and device design based on geometry and process considerations for 14 / 16 - nm FinFETs stress engineering. IEEE Transactions on Electron Devices. 2016;63(3):974–981.

Hoeneisen B and Mad CA. Fundamental Limitation in Microelectronics –I.MOS Technology. Solid-State Electronics. 1972;15:819–829.

Hagiwara T, Yamaguchi K and Asai S. Threshold voltage variation in very small MOS transistors due to local dopant fluctuations. Proceeding Symposium on VLSI Technology Digest of Technical Papers. 1982;46–47.

Asenov A. Statistically reliable 'Atomistic’ simulation of Sub 100nm MOSFETs. Simulation of Semiconductor Process and Devices. 1998;223–226.

Asenov A, Brown AR, Davies JH, Kaya S and Slavcheva G. Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs. IEEE Transactions on Devices. 2003;50(9):1837–1852.

Asenov A, Kaya S and Davies JH. Intrinsic Threshold Voltage fluctuations in Decanano MOSFETs Due to Local Oxide Thickness Variations. IEEE Transactions on Devices. 2002;49(1):112–119.

Asenov A, Kaya S and Brown AR. Intrinsic Parameter Fluctuations in Decananometer MOSFETs Introduced by Gate Line Edge Roughness. IEEE Transactions on Devices. 2003;50(5):1254–1260.

Yussoff AR, Suffian MRZM and Taib MY. Literature Review of Optimization Techniques for Chatter Suppression in Machining. Journal of Mechanical Engineering and Sciences. 2011;1:47–61.

Salehuddin F, Kaharudin KE, Zain ASM, Yamin AKM, and Ahmad I. Analysis of process parameter effect on DIBL in n-channel MOSFET device using L27 orthogonal array. International Conferences on Fundamental and Applied Sciences. 2014;1621(1):322–328.

Kaharudin KE, Salehuddin F, Zain ASM and Aziz MNIA. Optimization of Process Parameter Variations on Leakage Current in Silicon-on-insulator Vertical Double Gate Mosfet Device. Journal of Mechanical Engineering and Sciences. 2015;9:1614–1627.

Afifah Maheran AH, Menon PS, Ahmad I, and Shaari S. Optimisation of Process Parameters for Lower Leakage Current in 22 nm n-type MOSFET Device using Taguchi Method. Jurnal Teknologi. 2014;68(4):1–5.

Kaharudin KE, Salehuddin F, Zain ASM and Aziz MNIA. Taguchi Modeling With The Interaction Test For Higher Drive Current in WSix/TiO2 Channel Vertical Double Gate NMOS Device. Journal of Theoretical and Applied Information Technology. 2016; 90(1):185–193.

Aziz MNIA, Salehuddin F, Zain ASM, Kaharudin KE, Hazura H, Idris SK, Hanim AR and Manap Z. Analyze of threshold voltage in SOI PMOSFET device using Taguchi method. IEEE International Conference on Semiconductor Electronics (ICSE), 2016;97–100.

Faizah ZAN, Ahmad I, Ker PJ, Menon PS, and A. Meheran AH. VTH and ILEAK Optimization Using Taguchi Method at 32nm Bilayer Graphene PMOS. Journal of Telecommunication, Electronic and Computer Engineering (JTEC). 2017;9(2):105–109.

Othman NAF, Azhari FN, Hatta SFWM and Soin N. The Application of Taguchi Method on the Robust Optimization of p-FinFET Device Parameters. IEEE International Conference on Semiconductor Electronics (ICSE). 2016;141–144.

Jamaluddin H, Jaharah AG, Deros BM, Nizam ARM, and Rizauddin R. Quality improvement using Taguchi method in shot blasting process. Journal of Mechanical Engineering and Sciences. 2016;10(2):2200–2213.

Parate PR and Yarasu RB. Application of Taguchi and ANOVA in Optimization of Process Parameters of Lapping Operation for Cast Iron. Journal of Mechanical Engineering and Sciences. 2013;4:479–487.

Prayogo GS and Lusi N. Application of Taguchi technique coupled with grey relational analysis for multiple performance characteristics optimization of EDM parameters on ST 42 steel. AIP Conference Proceedings, 2016;1725:020061-1-020061-7.

Sekhar VC, Hussain SA, Pandurangadu V and Rao TS. Grey Relational Analysis to Determine Optimum Process Parameters of „ Emu ‟ Feather Fiber Reinforced Epoxy Composites. International Journal of Emerging Technology and Advanced Engineering. 2015;5(8):86–90.

Nayak S and Routara BC. Optimization Of Multiple Performance Characteristics In Electro Discharge Machining Using Grey Relational Analysis. International Journal of Scientific & Technology Research. 2014;3(4):116–121.

Sukhdeve V and Ganguly SK. Utility of Taguchi Based Grey Relational Analysis to optimize any Process or System. International Journal of Advanced Engineering Research and Studies. 2015;Jan-March:242–250.

Shivapragash B, Chandrasekaran K, Parthasarathy C and Samuel M. Multiple Response Optimizations in Drilling Using Taguchi and Grey Relational Analysis. International Journal of Modern Engineering Research (IJMER). 2013;3(2):765–768.

Lin HL. The use of the Taguchi method with grey relational analysis and a neural network to optimize a novel GMA welding process. Journal of Intelligent Manufacturing. 2012;23:1671–1680.

Kaharudin KE, Salehuddin F, Zain ASM and Aziz MNIA. Application of Taguchi-based Grey Fuzzy Logic for Simultaneous Optimization in TiO2/WSix-based Vertical double-gate MOSFET. Journal of Telecommunication, Electronic and Computer Engineering. 2017;9(2–13):23–28.

Kaharudin KE, Salehuddin F, Zain ASM, Aziz MNIA, Manap Z, Salam NAA and Saad WHM. Multi-response optimization in vertical double gate PMOS device using Taguchi method and grey relational analysis. IEEE International Conference on Semiconductor Electronics (ICSE). 2016;64–68.

Kenghe KR and Patare PM. Optimization of Tribological Properties Using Grey Relational Analysis and Artificial Neural Network. International Engineering Research Journal. 2015;1(1):1022–1028.

Kaharudin KE, Salehuddin F and Zain ASM. Optimization of Electrical Properties in TiO2/WSix-based Vertical DG-MOSFET using Taguchi-based GRA with ANN. Journal of Telecommunication, Electronic and Computer Engineering. 2018;10(1):69–76.

Noor CWM, Mamat R, Najafi G, Yasin MHM, Ihsan CK and Noor MM. Prediction of marine diesel engine performance by using artificial neural network model. Journal of Mechanical Engineering and Sciences. 2016;10(1):1917–1930.

Chau R, Brask J, Datta S, Dewey G, Doczy M, Doyle B, Kavalieros J, Jin B, Metz M, Majumdar A and Radosavljevic M. Application of high-k gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology. Microelectronic Engineering. 2015;80:1–6.

Chau R, Datta S, Doczy M, Doyle B, Kavalieros J and Metz M. High-k/metal-gate stack and its MOSFET characteristics. IEEE Electron Device Letters. 2004;25(6):408–410.

Silvaco. Silvaco ATLAS manual Device Simulation Software. 2006.