Experimental evaluation on the silicon mechanical performance of electronic packaging

W. Fong; K.L. Koay; I.A. Azid

doi:10.15282/jmes.11.1.2017.5.0226

Authors

W. Fong UNIKL, Malaysian Spanish Institution, Kulim, Kedah, Malaysia
K.L. Koay UNIKL, Malaysian Spanish Institution, Kulim, Kedah, Malaysia
I.A. Azid UNIKL, Malaysian Spanish Institution, Kulim, Kedah, Malaysia

DOI:

https://doi.org/10.15282/jmes.11.1.2017.5.0226

Keywords:

Semiconductor package; silicon break strength; 3-point bend; reliability; mechanical performance; laser marking.

Abstract

Semiconductor packaging is trending towards a miniaturisation in size but an increase in functionality. Hence, the thickness of the silicon wafer has decreased dramatically with a concern on the possible degradation of the strength of the thinned wafer. In this paper, 3-point bend (3PB) on bare silicon is selected as the preferred silicon break strength (SBS) test methodology due to its setup effectiveness and subsequent application in the prediction study. This experimental testing study focused on evaluating the SBS from different thickness ranges. The study was then followed by evaluating the influence of a possible impact from flaw creation with laser marking on silicon surfaces. The results show that the SBS is consistent although with significant differences in the silicon thickness ranges. It is also revealed that the onset breaking load may not be a suitable metric and could be over sensitive on gauging the SBS comparison. The flaw creation from the engraving process revealed a significant drop of 75% SBS although with an approximate depth removal of <10% from the total thickness. The consistence failure mode is clearly visible and this left the silicon very vulnerable to catastrophic failure. This indicates that extra care is needed on ultra-thin silicon during the assembly process as fractures may happen even before any reliability stress test is conducted. Furthermore, the completion of the package level 3PB failure mode verification has helped to demonstrate that an SBS study can be conducted with a simplified bare silicon level testing. In short, the study with this simplified 3PB has successfully proven its usefulness in SBS estimation. The observed ultra-thin silicon SBS has degraded and strongly depended on the critical flaws especially from the surface defect and impact from the assembly handling.

References

Szendiuch I. Development in electronic packaging–moving to 3D system configuration. Radioengineering. 2011;20:214-20.

Nakamura Y, Katogi S. Technology trends and future history of semiconductor packaging substrate material. Hitachi Chemical review (6). 2013.

Priyabadini S. 3D-stacking of ultra-thin chips and chip packages: Ghent University; 2013.

Garrou P, Koyanagi M, Ramm P. Handbook of 3D Integration, Volume 3: 3D Process Technology: John Wiley & Sons; 2014.

Takahashi Y, Nogawa H, Morozumi A, Nishimura Y. The latest package and assembly technology for SiC power module. IEEE CPMT Symposium Japan. 2016. p. 1-4.

Hsieh M-C. Advanced flip chip package on package technology for mobile applications. IEEE 17th International Conference on Electronic Packaging Technology. 2016. p. 486-91.

Standards SI. SEMI G86-0303 - Test method for measurement of chip (Die) strength by mean of 3-point bending. Japanese Regional Standards Committee; 2003.

Chengalva MK. Flip chip die cracking-a simplified approach utilizing experimentation and simulations. The Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems. 2002; p. 876-83.

Wu J, Huang C, Liao C. Fracture strength characterization and failure analysis of silicon dies. Microelectronics Reliability. 2003;43:269-77.

Chong DY, Lee W, Lim B, Pang JH, Low T. Mechanical characterization in failure strength of silicon dice. The Ninth Intersociety Conference on IEEE Thermal and Thermomechanical Phenomena in Electronic Systems. 2004; p. 203-10.

Tsai M, Chen C. Evaluation of test methods for silicon die strength. Microelectronics Reliability. 2008;48:933-41.

Yeung B, Lee T-Y. An overview of experimental methodologies and their applications for die strength measurement. IEEE Transactions on Components and Packaging Technologies. 2003;26:423-8.

Sun W, Zhu W, Che F, Wang C, Sun AY, Tan H. Ultra-thin die characterization for stack-die packaging. Proceedings 0f 57th IEEE Electronic Components and Technology Conference. 2007; p. 1390-6.

Wu C, Hsieh M, Chiang K. Strength evaluation of silicon die for 3D chip stacking packages using ABF as dielectric and barrier layer in through-silicon via. Microelectronic Engineering. 2010;87:505-9.

Zhao J-H, Tellkamp J, Gupta V, Edwards D. Experimental evaluations of the strength of silicon die by 3-point-bend versus ball-on-ring tests. 11th Intersociety Conference on: IEEE Thermal and Thermomechanical Phenomena in Electronic Systems. 2008; p. 687-94.

Guojun H, Jing-en L, Baraton X. Characterization of silicon die strength with application to die crack analysis. 33rd IEEE/CPMT International IEEE Electronic Manufacturing Technology Symposium. 2008; pp. 1-7.

Barnat S, Frémont H, Gracia A, Cadalen E. Evaluation by three-point-bend and ball-on-ring tests of thinning process on silicon die strength. Microelectronics Reliability. 2012;52:2278-82.

Garagorri J, Gorostegui-Colinas E, Elizalde M, Allen D, McNally P. Nanoindentation induced silicon fracture and 3D modelling. Anales de Mecánica de la Fractura. 2010. p. 559-64.

Echizenya D, Sasaki K. Effect of surface damage on strength of silicon wafer for solar cells. International Conference on IEEE Electronics Packaging. 2014; pp. 14-8.

Cotterell B, Chen Z, Han J, Tan N. The strength of the silicon die in flip-chip assemblies. 2003.

Tsai M, Lin C. Determination of silicon die strength. Proceedings of 55th IEEE Electronic Components and Technology Conference, 2005; pp. 1155-62.

Kroninger W, Mariani F. Thinning and singulation of silicon: Root causes of the damage in thin chips. Proceedings 56th IEEE Electronic Components and Technology Conference. 2006; pp. 1-6.

Schonfelder S, Ebert M, Bagdahn J. Influence of the thickness of silicon dies on strength. 7th International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems. 2006; p. 1-6.

Cook R. Strength and sharp contact fracture of silicon. Journal of Materials Sciences. 2006;41:841-72.

Janssen G, Abdalla M, Van Keulen F, Pujada B, Van Venrooy B. Celebrating the 100th anniversary of the Stoney equation for film stress: Developments from polycrystalline steel strips to single crystal silicon wafers. Thin Solid Films. 2009;517:1858-67.

Chen J, De Wolf I. Study of damage and stress induced by backgrinding in Si wafers. Semiconductor Science and Technology. 2003;18:261.

Sobotova L, Demec P. Laser marking of metal materials. Carbon. 2015;26:59.

vom Bauer U, Müller J, Patzlaff T, Binder D, Geissler S, Spallek M, et al. Laser marking of silicon solar cells in mass production. Proceedings of 25th EU-PVSEC, Valencia, Spain. 2010.

Hayashi K. Laser marking method and apparatus, and marked member. Google Patents; 2001.

Gu B. Latest development in chip scale package laser marking and micro laser marking. IEEE 29th International Electronics Manufacturing Technology Symposium. 2004; p. 144-6.

Khoong L, Lam Y, Zheng H, Chen X. Laser soft marking on silicon wafer. Journal of Appllied Physics. 2010;107:053107.

Hulusic V, Harvey C, Debattista K, Tsingos N, Walker S, Howard D, et al. Acoustic rendering and auditory–visual cross‐modal perception and interaction. Computer Graphics Forum: Wiley Online Library; 2012. p. 102-31.

Jiun HH, Ahmad I, Jalar A, Omar G. Effect of wafer thinning methods towards fracture strength and topography of silicon die. Microelectronics Reliability. 2006;46:836-45.

Lau K, Wu J. Effects of wafer thinning condition on the roughness, morphology and fracture strength of silicon die. Journal of Electronic Packaging. 2004; 126(1){110-4.

Takyu S, Kurosawa T, Shimizu N, Harada S. Novel wafer dicing and chip thinning technologies realizing high chip strength. Proceedings. 56th Electronic Components and Technology Conference. 2006. 970-4.

Bie X, Qin F, Zhou L, Sun J, Chen P, Wang Z. Impacts of back-grinding process parameters on the strength of thinned silicon wafer. IEEE 17th International Conference on Electronic Packaging Technology. 2016; p. 1197-200.

Marks MR, Hassan Z, Cheong KY. Effect of nanosecond laser dicing on the mechanical strength and fracture mechanism of ultrathin Si dies with Cu stabilization layer. IEEE Transactions on Components, Packaging and Manufacturing Technology. 2015;5:1885-97.

Feng X, Huang Y, Rosakis A. On the Stoney formula for a thin film/substrate system with nonuniform substrate thickness. Journal of Applied Mechanics. 2007;74:1276-81.

Shiradkar N, Seigneur H, Newton TR, Danyluk S, Schoenfeld WV. Effect of laser marks and residual stress in wafers on the propensity for performance loss due to cracking in solar cells. IEEE 43rd Photovoltaic Specialists Conference. 2016; p. 0708-12.

Hooper A, Ehorn J, Brand M, Bassett C. Review of wafer dicing techniques for via-middle process 3DI/TSV ultrathin silicon device wafers. IEEE 65th Electronic Components and Technology Conference. 2015. p. 1436-46.

VKX Series Brochure, July 2015, http://www.keyence.com.